Clock and Data Recovery (CDR)
The core of a retimer is its CDR circuit, which extracts the clock from the incoming data stream and retimes the signal, effectively resetting the jitter budget.
Full Signal Regeneration
It uses equalization (both CTLE and DFE) to clean the incoming signal before retransmitting a completely fresh copy, correcting for both deterministic and random jitter, crosstalk, and lane-to-lane skew.
Protocol Awareness
As a protocol-aware component, a retimer participates in link training (LTSSM), allowing it to adapt its equalizers to optimize the connection between two endpoints.
Use Case
Necessary for high-speed, demanding applications like AI infrastructure, data centers, and any system using PCIe 4.0, 5.0, and 6.0, especially over longer channels or multi-connector topologies.
Equalization
A redriver primarily uses a Continuous Time Linear Equalizer (CTLE) to compensate for frequency-dependent attenuation from PCB traces and cables, effectively opening the signal's eye.
Amplification
It boosts the entire signal to extend its reach. Since it is a non-protocol-aware device, it does not differentiate between the signal and any noise it carries.
Benefits
Lower cost, minimal power consumption, and very low latency (typically around 100ps).
Use Case
Best suited for less complex systems or lower data rates (e.g., PCIe Gen 3) where signal degradation is moderate and primarily deterministic.
